Datasheet

Configuration Registers (CONFIG)
MC68HC908LJ12 — Rev. 2.1 Technical Data
Freescale Semiconductor Configuration Registers (CONFIG) 73
5.4 Configuration Register 1 (CONFIG1)
COPRS — COP Rate Select
COPRS selects the COP time-out period. Reset clears COPRS. (See
Section 20. Computer Operating Properly (COP).)
1 = COP time out period = 2
13
– 2
4
ICLK cycles
0 = COP time out period = 2
18
– 2
4
ICLK cycles
LVISTOP — LVI Enable in Stop Mode
When the LVIPWRD bit is clear, setting the LVISTOP bit enables the
LVI to operate during stop mode. Reset clears LVISTOP. (See
Section 21. Low-Voltage Inhibit (LVI).)
1 = LVI enabled during stop mode
0 = LVI disabled during stop mode
LVIRSTD — LVI Reset Disable
LVIRSTD disables the reset signal from the LVI module. (See
Section 21. Low-Voltage Inhibit (LVI).)
1 = LVI module resets disabled
0 = LVI module resets enabled
LVIPWRD — LVI Power Disable Bit
LVIPWRD disables the LVI module. (See Section 21. Low-Voltage
Inhibit (LVI).) Reset sets LVIPWRD.
1 = LVI module power disabled
0 = LVI module power enabled
Address: $001F
Bit 7654321Bit 0
Read:
COPRS LVISTOP LVIRSTD LVIPWRD
0
SSREC STOP COPD
Write:
Reset:00010000
= Unimplemented
Figure 5-2. Configuration Register 1 (CONFIG1)