Datasheet

Electrical Specifications
MC68HC908LJ12 — Rev. 2.1 Technical Data
Freescale Semiconductor Electrical Specifications 403
23.17 3.3V SPI Characteristics
Diagram
Number
(1)
Notes:
1. Numbers refer to dimensions in Figure 23-1 and Figure 23-2.
Characteristic
(2)
2. All timing is shown with respect to 20% V
DD
and 70% V
DD
, unless noted; 100 pF load on all SPI pins.
Symbol Min Max Unit
Operating frequency
Master
Slave
f
OP(M)
f
OP(S)
f
OP
/128
dc
f
OP
/2
f
OP
MHz
MHz
1
Cycle time
Master
Slave
t
CYC(M)
t
CYC(S)
2
1
128
—
t
CYC
t
CYC
2 Enable lead time t
Lead(s)
1—t
CYC
3 Enable lag time t
Lag(s)
1—t
CYC
4
Clock (SPSCK) high time
Master
Slave
t
SCKH(M)
t
SCKH(S)
t
CYC
–35
1/2 t
CYC
–35
64 t
CYC
—
ns
ns
5
Clock (SPSCK) low time
Master
Slave
t
SCKL(M)
t
SCKL(S)
t
CYC
–35
1/2 t
CYC
–35
64 t
CYC
—
ns
ns
6
Data setup time (inputs)
Master
Slave
t
SU(M)
t
SU(S)
40
40
—
—
ns
ns
7
Data hold time (inputs)
Master
Slave
t
H(M)
t
H(S)
40
40
—
—
ns
ns
8
Access time, slave
(3)
CPHA = 0
CPHA = 1
3. Time to data active from high-impedance state
t
A(CP0)
t
A(CP1)
0
0
50
50
ns
ns
9 Disable time, slave
(4)
4. Hold time to high-impedance state
t
DIS(S)
—50ns
10
Data valid time, after enable edge
Master
Slave
(5)
5. With 100 pF on all SPI pins
t
V(M)
t
V(S)
—
—
60
60
ns
ns
11
Data hold time, outputs, after enable edge
Master
Slave
t
HO(M)
t
HO(S)
0
0
—
—
ns
ns