Datasheet
Electrical Specifications
MC68HC908LJ12 — Rev. 2.1 Technical Data
Freescale Semiconductor Electrical Specifications 397
23.8 5.0V Control Timing
23.9 3.3V Control Timing
Notes:
1. V
DD
= 3.0 to 3.6 Vdc, V
SS
= 0 Vdc, T
A
= T
L
to T
H
, unless otherwise noted.
2. Typical values reflect average measurements at midpoint of voltage range, 25 °C only.
3. Run (operating) I
DD
measured using external square wave clock source. All inputs 0.2 V from rail. No dc loads. Less than
100 pF on all outputs. C
L
= 20 pF on OSC2. All ports configured as inputs. OSC2 capacitance linearly affects run I
DD
.
4. Wait I
DD
measured using external square wave clock source. All inputs 0.2 V from rail. No dc loads. Less than 100 pF on
all outputs. C
L
= 20 pF on OSC2. All ports configured as inputs. OSC2 capacitance linearly affects wait I
DD
.
5. The 8kHz clock is from a 32kHz clock input at OSC1, for the driving the RTC.
6. LCD driver configured for high current mode.
7. Maximum is highest voltage that POR is guaranteed.
8. If minimum V
DD
is not reached before the internal POR reset is released, RST must be driven low externally until minimum
V
DD
is reached.
9. R
PU1
and
R
PU2
are measured at
V
DD
= 3.3V.
Table 23-6. 5.0V Control Timing
Characteristic
(1)
Notes:
1. V
SS
= 0 Vdc; timing shown with respect to 20% V
DD
and 70% V
DD
, unless otherwise noted.
Symbol Min Max Unit
Internal operating frequency
(2)
2. Some modules may require a minimum frequency greater than dc for proper operation; see appropriate table for this
information.
f
OP
—8MHz
RST
input pulse width low
(3)
3. Minimum pulse width reset is guaranteed to be recognized. It is possible for a smaller pulse width to cause a reset.
t
IRL
750 — ns
Table 23-7. 3.3V Control Timing
Characteristic
(1)
Notes:
1. V
SS
= 0 Vdc; timing shown with respect to 20% V
DD
and 70% V
DD
, unless otherwise noted.
Symbol Min Max Unit
Internal operating frequency
(2)
2. Some modules may require a minimum frequency greater than dc for proper operation; see appropriate table for this
information.
f
OP
—4MHz
RST
input pulse width low
(3)
3. Minimum pulse width reset is guaranteed to be recognized. It is possible for a smaller pulse width to cause a reset.
t
IRL
1.5 — µs