Datasheet

Low-Voltage Inhibit (LVI)
MC68HC908LJ12 — Rev. 2.1 Technical Data
Freescale Semiconductor Low-Voltage Inhibit (LVI) 381
21.4.4 LVI Trip Selection
The trip point selection bits, LVISEL[1:0], in the CONFIG2 register select
whether the LVI is configured for 5V or 3.3 V operation. (See Section 5.
Configuration Registers (CONFIG).)
NOTE: The MCU is guaranteed to operate at a minimum supply voltage. The trip
point (V
TRIPF
[5 V] or V
TRIPF
[3.3 V]) may be lower than this. (See
Section 23. Electrical Specifications for the actual trip point voltages.)
21.5 LVI Status Register
The LVI status register (LVISR) controls LVI interrupt functions and
indicates if the V
DD
voltage was detected below the V
TRIPF
level.
LVIOUT — LVI Output Bit
This read-only flag becomes set when the V
DD
voltage falls below the
V
TRIPF
trip voltage (see Table 21-2). Reset clears the LVIOUT bit.
Address: $FE0F
Bit 7654321Bit 0
Read: LVIOUT
LVIIE
LVIIF00000
Write:
LVIIAK
Reset:00000000
= Unimplemented
Table 21-1. LVI Status Register (LVISR)
Table 21-2. LVIOUT Bit Indication
V
DD
LVIOUT
V
DD
> V
TRIPR
0
V
DD
< V
TRIPF
1
V
TRIPF
< V
DD
< V
TRIPR
Previous value