Datasheet

Computer Operating Properly (COP)
MC68HC908LJ12 — Rev. 2.1 Technical Data
Freescale Semiconductor Computer Operating Properly (COP) 375
20.5 COP Control Register
The COP control register is located at address $FFFF and overlaps the
reset vector. Writing any value to $FFFF clears the COP counter and
starts a new timeout period. Reading location $FFFF returns the low
byte of the reset vector.
20.6 Interrupts
The COP does not generate CPU interrupt requests.
20.7 Monitor Mode
When monitor mode is entered with V
TST
on the IRQ pin, the COP is
disabled as long as V
TST
remains on the IRQ pin or the RST pin. When
monitor mode is entered by having blank reset vectors and not having
V
TST
on the IRQ pin, the COP is automatically disabled until a POR
occurs.
20.8 Low-Power Modes
The WAIT and STOP instructions put the MCU in low
power-consumption standby modes.
Address: $FFFF
Bit 7654321Bit 0
Read: Low byte of reset vector
Write: Clear COP counter
Reset: Unaffected by reset
Figure 20-3. COP Control Register (COPCTL)