Datasheet

Computer Operating Properly (COP)
Technical Data MC68HC908LJ12 — Rev. 2.1
372 Computer Operating Properly (COP) Freescale Semiconductor
20.3 Functional Description
Figure 20-1 shows the structure of the COP module.
Figure 20-1. COP Block Diagram
The COP counter is a free-running 6-bit counter preceded by a 12-bit
prescaler counter. If not cleared by software, the COP counter overflows
and generates an asynchronous reset after 2
18
–2
4
or 2
13
–2
4
ICLK
cycles, depending on the state of the COP rate select bit, COPRS, in the
CONFIG1 register. With a 2
13
–2
4
ICLK cycle overflow option, a 47-kHz
ICLK gives a COP timeout period of 174ms. Writing any value to location
$FFFF before an overflow occurs prevents a COP reset by clearing the
COP counter and stages 12 through 5 of the prescaler.
NOTE: Service the COP immediately after reset and before entering or after
exiting STOP Mode to guarantee the maximum time before the first COP
counter overflow.
COPCTL WRITE
ICLK
RESET VECTOR FETCH
RESET CIRCUIT
RESET STATUS REGISTER
INTERNAL RESET SOURCES
12-BIT COP PRESCALER
CLEAR ALL STAGES
6-BIT COP COUNTER
COP DISABLE
RESET
COPCTL WRITE
CLEAR
COPEN (FROM SIM)
COP COUNTER
COP CLOCK
COP TIMEOUT
STOP INSTRUCTION
(COPD FROM CONFIG1)
COP RATE SEL
(COPRS FROM CONFIG1)
CLEAR STAGES 5–12