Datasheet

External Interrupt (IRQ)
Technical Data MC68HC908LJ12 — Rev. 2.1
362 External Interrupt (IRQ) Freescale Semiconductor
IRQF — IRQ Flag Bit
This read-only status bit is high when the IRQ interrupt is pending.
1 = IRQ interrupt pending
0 = IRQ interrupt not pending
ACK — IRQ Interrupt Request Acknowledge Bit
Writing a logic 1 to this write-only bit clears the IRQ latch. ACK always
reads as logic 0. Reset clears ACK.
IMASK — IRQ Interrupt Mask Bit
Writing a logic 1 to this read/write bit disables IRQ interrupt requests.
Reset clears IMASK.
1 = IRQ interrupt requests disabled
0 = IRQ interrupt requests enabled
MODE — IRQ Edge/Level Select Bit
This read/write bit controls the triggering sensitivity of the IRQ
pin.
Reset clears MODE.
1 = IRQ
interrupt requests on falling edges and low levels
0 = IRQ
interrupt requests on falling edges only
Address: $001E
Bit 7654321Bit 0
Read: 0000IRQF0
IMASK MODE
Write:
ACK
Reset:00000000
= Unimplemented
Figure 18-2. IRQ Status and Control Register (INTSCR)