Datasheet

Input/Output (I/O) Ports
Technical Data MC68HC908LJ12 — Rev. 2.1
356 Input/Output (I/O) Ports Freescale Semiconductor
Figure 17-14. Port D I/O Circuit
When DDRDx is a logic 1, reading address $0003 reads the PTDx data
latch. When DDRDx is a logic 0, reading address $0003 reads the
voltage level on the pin. The data latch can always be written, regardless
of the state of its data direction bit.
Table 17-5 summarizes the operation of the port D pins.
Table 17-5. Port D Pin Functions
DDRD
Bit
PTD Bit
I/O Pin
Mode
Accesses
to DDRD
Accesses to PTD
Read/Write Read Write
0X
(1)
Notes:
1. X = don’t care.
Input, Hi-Z
(2)
2. Hi-Z = high impedance.
DDRD[7:0] Pin PTD[7:0]
(3)
3. Writing affects data register, but does not affect the input.
1 X Output DDRD[7:0] PTD[7:0] PTD[7:0]
READ DDRD ($0007)
WRITE DDRD ($0007)
RESET
WRITE PTD ($0003)
READ PTD ($0003)
PTDx
DDRDx
PTDx
INTERNAL DATA BUS