Datasheet

Input/Output (I/O) Ports
Technical Data MC68HC908LJ12 — Rev. 2.1
346 Input/Output (I/O) Ports Freescale Semiconductor
Figure 17-4. Port A I/O Circuit
When DDRAx is a logic 1, reading address $0000 reads the PTAx data
latch. When DDRAx is a logic 0, reading address $0000 reads the
voltage level on the pin. The data latch can always be written, regardless
of the state of its data direction bit.
Table 17-2 summarizes the operation of the port A pins.
Table 17-2. Port A Pin Functions
DDRA
Bit
PTA Bit I/O Pin Mode
Accesses to DDRA Accesses to PTA
Read/Write Read Write
0X
(1)
Notes:
1. X = don’t care.
Input, Hi-Z
(2)
2. Hi-Z = high impedance.
DDRA[7:0] Pin PTA[7:0]
(3)
3. Writing affects data register, but does not affect input.
1 X Output DDRA[7:0] PTA[7:0] PTA[7:0]
READ DDRA ($0004)
WRITE DDRA ($0004)
RESET
WRITE PTA ($0000)
READ PTA ($0000)
PTAx
DDRAx
PTAx
INTERNAL DATA BUS