Datasheet

Liquid Crystal Display Driver (LCD)
Technical Data MC68HC908LJ12 — Rev. 2.1
338 Liquid Crystal Display Driver (LCD) Freescale Semiconductor
DUTY[1:0] — Duty Cycle Select
These read/write bits select the duty cycle of the LCD driver output
waveforms. The multiplexed FP0/BP3 pin is controlled by the duty
cycle selected. Reset clears these bits.
LCLK[2:0] — LCD Waveform Base Clock Select
These read/write bits selects the LCD waveform base clock. Reset
clears these bits.
Table 16-5. LCD Duty Cycle Selection
DUTY1:DUTY0 Description
00 Static selected; FP0/BP3 pin function as FP0.
01 1/3 duty cycle selected; FP0/BP3 pin functions as FP0.
10 1/4 duty cycle selected; FP0/BP3 pin functions as BP3.
11 Not used
Table 16-6. LCD Waveform Base Clock Selection
LCLK2 LCLK1 LCLK0
Divide
Ratio
LCD Waveform Base
Clock Frequency
LCDCLK (Hz)
LCD Frame Rate
f
XTAL
(1)
=
32.768kHz
LCD Frame Rate
f
XTAL
=
4.9152MHz
f
XTAL
=
32.768kHz
f
XTAL
=
4.9152MHz
1/3
duty
1/4
duty
1/3
duty
1/4
duty
0 0 0 128 256 — 85.3 64 — —
0 0 1 256 128 — 42.7 32 — —
0 1 0 512 64 — 21.3 16 — —
0 1 1 1024 32 — 10.7 8 — —
1 0 0 16384 — 300 — — 100 75
1 0 1 32768 — 150 — — 50 37.5
1 1 0 65536 — 75 — — 25 18.75
111 Reserved
Notes:
1. f
XTAL
is the same as CGMXCLK (see Section 7. Oscillator (OSC)).