Datasheet

Liquid Crystal Display Driver (LCD)
MC68HC908LJ12 — Rev. 2.1 Technical Data
Freescale Semiconductor Liquid Crystal Display Driver (LCD) 323
16.5.2 LCD Voltages (V
LCD,
V
LCD1,
V
LCD2
, V
LCD3
)
The voltage V
LCD
is connected directly to V
DD
. V
LCD1
, V
LCD2
, and V
LCD3
are internal bias voltages for the LCD driver waveforms. They are
derived from V
LCD
using a resistor ladder (see Figure 16-3).
The relative potential of the LCD voltages are:
•V
LCD
= V
DD
•V
LCD1
= 2/3 × (V
LCD
– V
bias
)
•V
LCD2
= 1/3 × (V
LCD
– V
bias
)
•V
LCD3
= V
bias
The V
LCD3
bias voltage, V
bias
, is controlled by the LCD contrast control
bits, LCCON[2:0].
16.5.3 LCD Cycle Frame
The LCD driver module uses the CGMXCLK (see Section 7. Oscillator
(OSC)) as the input reference clock. This clock is divided to produce the
LCD waveform base clock, LCDCLK, by configuring the LCLK[2:0] bits
in the LCD clock register. The LCDCLK clocks the backplane and the
frontplane output waveforms.
The LCD cycle frame is determined by the equation:
For example, for 1/3 duty and 256Hz waveform base clock:
LCD CYCLE FRAME =
LCD WAVEFORM BASE CLOCK × DUTY
1
LCD CYCLE FRAME =
256 × (1/3)
1
= 11.72 ms