Datasheet

Analog-to-Digital Converter (ADC)
MC68HC908LJ12 — Rev. 2.1 Technical Data
Freescale Semiconductor Analog-to-Digital Converter (ADC) 315
If the external clock (CGMXCLK) is equal to or greater than 1MHz,
CGMXCLK can be used as the clock source for the ADC. If
CGMXCLK is less than 1MHz, use the PLL-generated bus clock as
the clock source. As long as the internal ADC clock is at f
ADIC
, correct
operation can be guaranteed.
1 = Internal bus clock
0 = External clock, CGMXCLK
MODE1 and MODE0 — Modes of Result Justification
MODE1 and MODE0 selects between four modes of operation. The
manner in which the ADC conversion results will be placed in the ADC
data registers is controlled by these modes of operation. Reset
returns right-justified mode.
Table 15-3. ADC Mode Select
MODE1 MODE0 ADC Clock Rate
0 0 8-bit truncated mode
0 1 Right justified mode
1 0 Left justified mode
1 1 Left justified sign data mode
CGMXCLK or bus frequency
f
ADIC
=
ADIV[2:0]