Datasheet

Analog-to-Digital Converter (ADC)
Technical Data MC68HC908LJ12 — Rev. 2.1
314 Analog-to-Digital Converter (ADC) Freescale Semiconductor
15.8.3 ADC Clock Control Register
The ADC clock control register (ADCLK) selects the clock frequency for
the ADC.
ADIV[2:0] — ADC Clock Prescaler Bits
ADIV2, ADIV1, and ADIV0 form a 3-bit field which selects the divide
ratio used by the ADC to generate the internal ADC clock.
Table 15-2 shows the available clock configurations. The ADC clock
should be set to between 32kHz and 2MHz.
ADICLK — ADC Input Clock Select Bit
ADICLK selects either bus clock or CGMXCLK as the input clock
source to generate the internal ADC clock. Reset selects CGMXCLK
as the ADC clock source.
Address: $003F
Read:
ADIV2 ADIV1 ADIV0 ADICLK MODE1 MODE0
00
Write:
R
Reset:00000100
= Unimplemented R = Reserved
Figure 15-9. ADC Clock Control Register (ADICLK)
Table 15-2. ADC Clock Divide Ratio
ADIV2 ADIV1 ADIV0 ADC Clock Rate
0 0 0 ADC input clock ÷ 1
0 0 1 ADC input clock ÷ 2
0 1 0 ADC input clock ÷ 4
0 1 1 ADC input clock ÷ 8
1 X X ADC input clock ÷ 16
X = don’t care