Datasheet

Analog-to-Digital Converter (ADC)
MC68HC908LJ12 — Rev. 2.1 Technical Data
Freescale Semiconductor Analog-to-Digital Converter (ADC) 313
In left justified mode the ADRH holds the eight most significant bits
(MSBs), and the ADRL holds the two least significant bits (LSBs), of the
10-bit result. The ADRH and ADRL are updated each time a single
channel ADC conversion completes. Reading ADRH latches the
contents of ADRL. Until ADRL is read all subsequent ADC results will be
lost. (See Figure 15-7 . ADRH and ADRL in Left Justified Mode.)
In left justified sign mode the ADRH holds the eight MSBs with the MSB
complemented, and the ADRL holds the two least significant bits (LSBs),
of the 10-bit result. The ADRH and ADRL are updated each time a single
channel ADC conversion completes. Reading ADRH latches the
contents of ADRL. Until ADRL is read all subsequent ADC results will be
lost. (See Figure 15-8 . ADRH and ADRL in Left Justified Sign Data
Mode.)
Addr.Register Name Bit 7654321Bit 0
$003D
ADC Data Register High
(ADRH)
Read: AD9 AD8 AD7 AD6 AD5 AD4 AD3 AD2
Write:RRRRRRRR
Reset:00000000
$003E
ADC Data Register Low
(ADRL)
Read: AD1 AD0 000000
Write:RRRRRRRR
Reset:00000000
Figure 15-7. ADRH and ADRL in Left Justified Mode
Addr.Register Name Bit 7654321Bit 0
$003D
ADC Data Register High
(ADRH)
Read: AD9
AD8 AD7 AD6 AD5 AD4 AD3 AD2
Write:RRRRRRRR
Reset:00000000
$003E
ADC Data Register Low
(ADRL)
Read: AD1 AD0 000000
Write:RRRRRRRR
Reset:00000000
Figure 15-8. ADRH and ADRL in Left Justified Sign Data Mode