Datasheet

Analog-to-Digital Converter (ADC)
Technical Data MC68HC908LJ12 — Rev. 2.1
310 Analog-to-Digital Converter (ADC) Freescale Semiconductor
15.8 I/O Registers
These I/O registers control and monitor operation of the ADC:
• ADC status and control register, ADSCR
• ADC data register, ADRH:ADRL
• ADC clock register, ADCLK
15.8.1 ADC Status and Control Register
This section describes the function of the ADC status and control
register (ADSCR). Writing ADSCR aborts the current conversion and
initiates a new conversion.
COCO — Conversions Complete Bit
When the AIEN bit is a logic 0, the COCO is a read-only bit which is
set each time a conversion is completed. This bit is cleared whenever
the ADSCR is written, or whenever the ADC clock control register is
written, or whenever the ADC data register low, ADRL, is read.
If the AIEN bit is logic 1, the COCO bit always read as logic 0, CPU to
service the ADC interrupt will be generated at the end if an ADC
conversion. Reset clears the COCO bit.
1 = Conversion completed (AIEN = 0)
0 = Conversion not completed (AIEN = 0)/CPU interrupt (AIEN=1)
AIEN — ADC Interrupt Enable Bit
When this bit is set, an interrupt is generated at the end of an ADC
conversion. The interrupt signal is cleared when the data register,
ADR0, is read or the ADSCR is written. Reset clears the AIEN bit.
1 = ADC interrupt enabled
0 = ADC interrupt disabled
Address: $003C
Read: COCO
AIEN ADCO ADCH4 ADCH3 ADCH2 ADCH1 ADCH0
Write:
Reset:00011111
= Unimplemented
Figure 15-4. ADC Status and Control Register (ADSCR)