Datasheet

Analog-to-Digital Converter (ADC)
Technical Data MC68HC908LJ12 — Rev. 2.1
308 Analog-to-Digital Converter (ADC) Freescale Semiconductor
15.5 Interrupts
When the AIEN bit is set, the ADC module is capable of generating a
CPU interrupt after each ADC conversion. A CPU interrupt is generated
if the COCO bit is at logic 0. The COCO bit is not used as a conversion
complete flag when interrupts are enabled. The interrupt vector is
defined in Table 2-1 . Vector Addresses.
15.6 Low-Power Modes
The STOP and WAIT instructions put the MCU in low power-
consumption standby modes.
15.6.1 Wait Mode
The ADC continues normal operation in wait mode. Any enabled CPU
interrupt request from the ADC can bring the MCU out of wait mode. If
the ADC is not required to bring the MCU out of wait mode, power down
the ADC by setting the ADCH[4:0] bits to logic 1’s before executing the
WAIT instruction.
15.6.2 Stop Mode
The ADC module is inactive after the execution of a STOP instruction.
Any pending conversion is aborted. ADC conversions resume when the
MCU exits stop mode. Allow one conversion cycle to stabilize the analog
circuitry before attempting a new ADC conversion after exiting stop
mode.
15.7 I/O Signals
The ADC module has nine channels, six channels are shared with port A
and port C I/O pins; two channels are the ADC voltage reference inputs,
V
REFH
and V
REFL
; and one channel is the 1.2V bandgap reference
voltage.