Datasheet

Analog-to-Digital Converter (ADC)
MC68HC908LJ12 — Rev. 2.1 Technical Data
Freescale Semiconductor Analog-to-Digital Converter (ADC) 305
15.4.2 Voltage Conversion
When the input voltage to the ADC equals V
REFH
, the ADC converts the
signal to $3FF (full scale). If the input voltage equals V
REFL
, the ADC
converts it to $000. Input voltages between V
REFH
and V
REFL
are
straight-line linear conversions. All other input voltages will result in
$3FF if greater than V
REFH
and $000 if less than V
REFL
.
NOTE: Input voltage should not exceed the analog supply voltages.
15.4.3 Conversion Time
Conversion starts after a write to the ADSCR. A conversion is between
16 and 17 ADC clock cycles, therefore:
The ADC conversion time is determined by the clock source chosen and
the divide ratio selected. The clock source is either the bus clock or
CGMXCLK and is selectable by the ADICLK bit located in the ADC clock
register. The divide ratio is selected by the ADIV[2:0] bits.
For example, if a 4MHz CGMXCLK is selected as the ADC input clock
source, with a divide-by-2 prescale, and the bus speed is set at 8MHz:
NOTE: The ADC frequency must be between f
ADIC
minimum and f
ADIC
maximum to meet ADC specifications. See 23.6 5.0V DC Electrical
Characteristics.
Since an ADC cycle may be comprised of several bus cycles (eight in the
previous example) and the start of a conversion is initiated by a bus cycle
write to the ADSCR, from zero to four additional bus cycles may occur
before the start of the initial ADC cycle. This results in a fractional ADC
cycle and is represented as the 17th cycle.
16 to17 ADC cycles
Conversion time =
ADC frequency
Number of bus cycles = conversion time × bus frequency
16 to 17 ADC cycles
Conversion time =
4MHz ÷ 2
Number of bus cycles = 8µs x 8MHz = 64 to 68 cycles
= 8 to 8.5 µs