Datasheet

Analog-to-Digital Converter (ADC)
MC68HC908LJ12 — Rev. 2.1 Technical Data
Freescale Semiconductor Analog-to-Digital Converter (ADC) 303
15.4 Functional Description
The ADC provides six pins for sampling external sources at pins
PTA4/ADC0–PTA7/ADC3 and PTB6/ADC4–PTB7/ADC5. An analog
multiplexer allows the single ADC converter to select one of nine ADC
channels as ADC voltage in (V
ADIN
). V
ADIN
is converted by the
successive approximation register-based analog-to-digital converter.
When the conversion is completed, ADC places the result in the ADC
data register, high and low byte (ADRH and ADRL), and sets a flag or
generates an interrupt.
Figure 15-2 shows the structure of the ADC module.
15.4.1 ADC Port I/O Pins
PTA4–PTA7 and PTB6–PTB7 are general-purpose I/O pins that are
shared with the ADC channels. The channel select bits, ADCH[4:0],
define which ADC channel/port pin will be used as the input signal. The
ADC overrides the port I/O logic by forcing that pin as input to the ADC.
The remaining ADC channels/port pins are controlled by the port I/O
Addr.Register Name Bit 7654321Bit 0
$003C
ADC Status and Control
Register
(ADSCR)
Read: COCO
AIEN ADCO ADCH4 ADCH3 ADCH2 ADCH1 ADCH0
Write:
Reset:00011111
$003D
ADC Data Register High
(ADRH)
Read: ADx ADx ADx ADx ADx ADx ADx ADx
Write:RRRRRRRR
Reset:00000000
$003E
ADC Data Register Low
(ADRL)
Read: ADx ADx ADx ADx ADx ADx ADx ADx
Write:RRRRRRRR
Reset:00000000
$003F
ADC Clock Register
(ADCLK)
Read:
ADIV2 ADIV1 ADIV0 ADICLK MODE1 MODE0
00
Write:
R
Reset:00000100
= Unimplemented R = Reserved
Figure 15-1. ADC I/O Register Summary