Datasheet
Serial Peripheral Interface Module (SPI)
Technical Data MC68HC908LJ12 — Rev. 2.1
282 Serial Peripheral Interface Module (SPI) Freescale Semiconductor
For an idle master or idle slave that has no data loaded into its transmit 
buffer, the SPTE is set again no more than two bus cycles after the 
transmit buffer empties into the shift register. This allows the user to 
queue up a 16-bit value to send. For an already active slave, the load of 
the shift register cannot occur until the transmission is completed. This 
implies that a back-to-back write to the transmit data register is not 
possible. The SPTE indicates when the next write can occur.
14.8 Error Conditions
The following flags signal SPI error conditions:
• Overflow (OVRF) — Failing to read the SPI data register before 
the next full byte enters the shift register sets the OVRF bit. The 
new byte does not transfer to the receive data register, and the 
unread byte still can be read. OVRF is in the SPI status and control 
register.
• Mode fault error (MODF) — The MODF bit indicates that the 
voltage on the slave select pin (SS) is inconsistent with the mode 
of the SPI. MODF is in the SPI status and control register.
14.8.1 Overflow Error
The overflow flag (OVRF) becomes set if the receive data register still 
has unread data from a previous transmission when the capture strobe 
of bit 1 of the next transmission occurs. The bit 1 capture strobe occurs 
in the middle of SPSCK cycle 7. (See Figure 14-4 and Figure 14-6.) If 
an overflow occurs, all data received after the overflow and before the 
OVRF bit is cleared does not transfer to the receive data register and 
does not set the SPI receiver full bit (SPRF). The unread data that 
transferred to the receive data register before the overflow occurred can 
still be read. Therefore, an overflow error always indicates the loss of 
data. Clear the overflow flag by reading the SPI status and control 
register and then reading the SPI data register.
OVRF generates a receiver/error CPU interrupt request if the error 
interrupt enable bit (ERRIE) is also set. The SPRF, MODF, and OVRF 










