Datasheet

List of Figures
MC68HC908LJ12 — Rev. 2.1 Technical Data
Freescale Semiconductor List of Figures 27
Figure Title Page
15-1 ADC I/O Register Summary . . . . . . . . . . . . . . . . . . . . . . . . . .303
15-2 ADC Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .304
15-3 8-Bit Truncation Mode Error . . . . . . . . . . . . . . . . . . . . . . . . . .307
15-4 ADC Status and Control Register (ADSCR). . . . . . . . . . . . . .310
15-5 ADRH and ADRL in 8-Bit Truncated Mode. . . . . . . . . . . . . . .312
15-6 ADRH and ADRL in Right Justified Mode. . . . . . . . . . . . . . . .312
15-7 ADRH and ADRL in Left Justified Mode. . . . . . . . . . . . . . . . .313
15-8 ADRH and ADRL in Left Justified Sign Data Mode . . . . . . . .313
15-9 ADC Clock Control Register (ADICLK). . . . . . . . . . . . . . . . . .314
16-1 LCD I/O Register Summary . . . . . . . . . . . . . . . . . . . . . . . . . .319
16-2 LCD Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .321
16-3 Simplified LCD Schematic (1/3 Duty, 1/3 Bias) . . . . . . . . . . .322
16-4 Fast Charge Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .324
16-5 1/3 Duty LCD Backplane Driver Waveforms. . . . . . . . . . . . . .326
16-6 Static LCD Backplane Driver Waveform. . . . . . . . . . . . . . . . .327
16-7 1/4 Duty LCD Backplane Driver Waveforms. . . . . . . . . . . . . .327
16-8 Static LCD Frontplane Driver Waveforms. . . . . . . . . . . . . . . .328
16-9 1/3 Duty LCD Frontplane Driver Waveforms . . . . . . . . . . . . .329
16-10 1/4 Duty LCD Frontplane Driver Waveforms . . . . . . . . . . . . .330
16-11 1/4 Duty LCD Frontplane Driver Waveforms (continued) . . . .331
16-12 7-Segment Display Example . . . . . . . . . . . . . . . . . . . . . . . . .332
16-13 BP0–BP2 and FP0–FP2 Output Waveforms for
7-Segment Display Example . . . . . . . . . . . . . . . . . . . . . . .333
16-14 "f" Segment Voltage Waveform . . . . . . . . . . . . . . . . . . . . . . .334
16-15 "e" Segment Voltage Waveform . . . . . . . . . . . . . . . . . . . . . . .334
16-16 LCD Control Register (LCDCR) . . . . . . . . . . . . . . . . . . . . . . .335
16-17 LCD Clock Register (LCDCLK). . . . . . . . . . . . . . . . . . . . . . . .337
16-18 LCD Data Registers 1–14 (LDAT1–LDAT14). . . . . . . . . . . . .339
17-1 I/O Port Register Summary. . . . . . . . . . . . . . . . . . . . . . . . . . .342
17-2 Port A Data Register (PTA) . . . . . . . . . . . . . . . . . . . . . . . . . .344
17-3 Data Direction Register A (DDRA) . . . . . . . . . . . . . . . . . . . . .345
17-4 Port A I/O Circuit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .346
17-5 Port B Data Register (PTB) . . . . . . . . . . . . . . . . . . . . . . . . . .347
17-6 Data Direction Register B (DDRB) . . . . . . . . . . . . . . . . . . . . .349
17-7 Port B I/O Circuit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .349