Datasheet

Infrared Serial Communications
Technical Data MC68HC908LJ12 — Rev. 2.1
258 Infrared Serial Communications Interface Module (IRSCI) Freescale Semiconductor
PEIE — Receiver Parity Error Interrupt Enable Bit
This read/write bit enables SCI receiver CPU interrupt
requests generated by the parity error bit, PE. (See 13.11.4 SCI
Status Register 1.) Reset clears PEIE.
1 = SCI error CPU interrupt requests from PE bit enabled
0 = SCI error CPU interrupt requests from PE bit disabled
13.11.4 SCI Status Register 1
SCI status register 1 contains flags to signal these conditions:
• Transfer of SCDR data to transmit shift register complete
• Transmission complete
• Transfer of receive shift register data to SCDR complete
• Receiver input idle
• Receiver overrun
• Noisy data
• Framing error
• Parity error
SCTE — SCI Transmitter Empty Bit
This clearable, read-only bit is set when the SCDR transfers a
character to the transmit shift register. SCTE can generate an SCI
transmitter CPU interrupt request. When the SCTIE bit in SCC2 is set,
SCTE generates an SCI transmitter CPU interrupt request. In normal
Address: $0016
Bit 7654321Bit 0
Read: SCTE TC SCRF IDLE OR NF FE PE
Write:
Reset:11000000
= Unimplemented
Figure 13-15. SCI Status Register 1 (SCS1)