Datasheet

Infrared Serial Communications Interface Module (IRSCI)

MC68HC908LJ12 — Rev. 2.1 Technical Data

Freescale Semiconductor Infrared Serial Communications Interface Module (IRSCI) 239

NOTE: When queueing an idle character, return the TE bit to logic 1 before the

stop bit of the current character shifts out to the TxD pin. Setting TE after

the stop bit appears on TxD causes data previously written to the SCDR

to be lost.

Toggle the TE bit for a queued idle character when the SCTE bit

becomes set and just before writing the next byte to the SCDR.

13.7.2.5 Transmitter Interrupts

The following conditions can generate CPU interrupt requests from the

SCI transmitter:

• SCI transmitter empty (SCTE) — The SCTE bit in SCS1 indicates

that the SCDR has transferred a character to the transmit shift

Setting the SCI transmit interrupt enable bit, SCTIE, in SCC2

enables the SCTE bit to generate transmitter CPU interrupt

requests.

• Transmission complete (TC) — The TC bit in SCS1 indicates that

the transmit shift register and the SCDR are empty and that no

break or idle character has been generated. The transmission

complete interrupt enable bit, TCIE, in SCC2 enables the TC bit to

generate transmitter CPU interrupt requests.

13.7.3 Receiver

Figure 13-8 shows the structure of the SCI receiver.

13.7.3.1 Character Length

The receiver can accommodate either 8-bit or 9-bit data. The state of the

M bit in SCI control register 1 (SCC1) determines character length.

When receiving 9-bit data, bit R8 in SCI control register 2 (SCC2) is the

ninth bit (bit 8). When receiving 8-bit data, bit R8 is a copy of the eighth

bit (bit 7).