Datasheet

Real Time Clock (RTC)
Technical Data MC68HC908LJ12 — Rev. 2.1
218 Real Time Clock (RTC) Freescale Semiconductor
12.6.2 RTC Control Register 2 (RTCCR2)
The RTC control register 2 (RTCCR2) contains control and clock
selection bits for RTC operation.
CHRCLR — Chronograph counter clear
Setting this write-only bit resets the chronograph counter. Setting
CHRCLR has no effect on any other registers. Counting resumes
from $00. CHRCLR is cleared automatically after the chronograph
counter is reset and always reads as logic 0. Reset clears the
CHRCLR bit.
1 = Chronograph counter cleared
0 = No effect
CHRE — Chronograph Enable
This read/write bit enables the chronograph counter, the value in the
chronograph data register increments by 1 in every 1/100 seconds.
When the chronograph counter is disabled (CHRE = 0), the value in
the chronograph data register is held at the count value. Reset clears
the CHRE bit.
1 = Chronograph counter enabled
0 = Chronograph counter disabled
RTCE — Real Time Clock Enable
This read/write bit enables the entire RTC module, allowing all RTC
and chronograph operations. Disabling the RTC module does not
affect the contents in the RTC registers. Reset clears the RTCE bit.
1 = RTC module enabled
0 = RTC module disabled
Address: $0043
Read: 0
0
CHRE RTCE
0
XTL2 XTL1 XTL0
Write: R CHRCLR
Reset:00000000
= Unimplemented R = Reserved
Figure 12-4. RTC Control Register 2 (RTCCR2)