Datasheet

Timer Interface Module (TIM)
Technical Data MC68HC908LJ12 — Rev. 2.1
206 Timer Interface Module (TIM) Freescale Semiconductor
When ELSxB:ELSxA = 0:0, this read/write bit selects the initial output
level of the TCHx pin. See Table 11-3. Reset clears the MSxA bit.
1 = Initial output level low
0 = Initial output level high
NOTE: Before changing a channel function by writing to the MSxB or MSxA bit,
set the TSTOP and TRST bits in the TIM status and control register
(TSC).
ELSxB and ELSxA — Edge/Level Select Bits
When channel x is an input capture channel, these read/write bits
control the active edge-sensing logic on channel x.
When channel x is an output compare channel, ELSxB and ELSxA
control the channel x output behavior when an output compare
occurs.
When ELSxB and ELSxA are both clear, channel x is not connected
to an I/O port, and pin TCHx is available as a general-purpose I/O pin.
Table 11-3 shows how ELSxB and ELSxA work. Reset clears the
ELSxB and ELSxA bits.
Table 11-3. Mode, Edge, and Level Selection
MSxB:MSxA ELSxB:ELSxA Mode Configuration
X0 00
Output preset
Pin under port control;
initial output level high
X1 00
Pin under port control;
initial output level low
00 01
Input capture
Capture on rising edge only
00 10 Capture on falling edge only
00 11
Capture on rising or
falling edge
01 01
Output
compare or
PWM
Toggle output on compare
01 10 Clear output on compare
01 11 Set output on compare
1X 01
Buffered
output
compare or
buffered PWM
Toggle output on compare
1X 10 Clear output on compare
1X 11 Set output on compare