Datasheet

Timer Interface Module (TIM)
Technical Data MC68HC908LJ12 — Rev. 2.1
204 Timer Interface Module (TIM) Freescale Semiconductor
11.10.4 TIM Channel Status and Control Registers
Each of the TIM channel status and control registers:
• Flags input captures and output compares
• Enables input capture and output compare interrupts
• Selects input capture, output compare, or PWM operation
• Selects high, low, or toggling output on output compare
• Selects rising edge, falling edge, or any edge as the active input
capture trigger
• Selects output toggling on TIM overflow
• Selects 0% and 100% PWM duty cycle
• Selects buffered or unbuffered output compare/PWM operation
Address: T1SC0, $0025 and T2SC0, $0030
Bit 7654321Bit 0
Read: CH0F
CH0IE MS0B MS0A ELS0B ELS0A TOV0 CH0MAX
Write: 0
Reset:00000000
Figure 11-9. TIM Channel 0 Status and Control Register (TSC0)
Address: T1SC1, $0028 and T2SC1, $0033
Bit 7654321Bit 0
Read: CH1F
CH1IE
0
MS1A ELS1B ELS1A TOV1 CH1MAX
Write: 0
Reset:00000000
= Unimplemented
Figure 11-10. TIM Channel 1 Status and Control Register (TSC1)