Datasheet

Timer Interface Module (TIM)
MC68HC908LJ12 — Rev. 2.1 Technical Data
Freescale Semiconductor Timer Interface Module (TIM) 199
11.9 I/O Signals
Port B shares four of its pins with the TIM. The four TIM channel I/O pins
are T1CH0, T1CH1, T2CH0, and T2CH1 as described in 11.4 Pin Name
Conventions.
Each channel I/O pin is programmable independently as an input
capture pin or an output compare pin. T1CH0 and T2CH0 can be
configured as buffered output compare or buffered PWM pins.
11.10 I/O Registers
NOTE: References to either timer 1 or timer 2 may be made in the following text
by omitting the timer number. For example, TSC may generically refer to
both T1SC AND T2SC.
These I/O registers control and monitor operation of the TIM:
• TIM status and control register (TSC)
• TIM counter registers (TCNTH:TCNTL)
• TIM counter modulo registers (TMODH:TMODL)
• TIM channel status and control registers (TSC0, TSC1)
• TIM channel registers (TCH0H:TCH0L, TCH1H:TCH1L)