Datasheet

Timer Interface Module (TIM)
Technical Data MC68HC908LJ12 — Rev. 2.1
190 Timer Interface Module (TIM) Freescale Semiconductor
$0029
Timer 1 Channel 1
Register High
(T1CH1H)
Read:
Bit 15 14 13 12 11 10 9 Bit 8
Write:
Reset: Indeterminate after reset
$002A
Timer 1 Channel 1
Register Low
(T1CH1L)
Read:
Bit 7654321Bit 0
Write:
Reset: Indeterminate after reset
$002B
Timer 2 Status and
Control Register
(T2SC)
Read: TOF
TOIE TSTOP
00
PS2 PS1 PS0
Write: 0 TRST
Reset:00100000
$002C
Timer 2 Counter
Register High
(T2CNTH)
Read: Bit 15 14 13 12 11 10 9 Bit 8
Write:
Reset:00000000
$002D
Timer 2 Counter
Register Low
(T2CNTL)
Read: Bit 7 654321Bit 0
Write:
Reset:00000000
$002E
Timer 2 Counter Modulo
Register High
(T2MODH)
Read:
Bit 15 14 13 12 11 10 9 Bit 8
Write:
Reset:11111111
$002F
Timer 2 Counter Modulo
Register Low
(T2MODL)
Read:
Bit 7654321Bit 0
Write:
Reset:11111111
$0030
Timer 2 Channel 0 Status
and Control Register
(T2SC0)
Read: CH0F
CH0IE MS0B MS0A ELS0B ELS0A TOV0 CH0MAX
Write: 0
Reset:00000000
$0031
Timer 2 Channel 0
Register High
(T2CH0H)
Read:
Bit 15 14 13 12 11 10 9 Bit 8
Write:
Reset: Indeterminate after reset
Addr.Register Name Bit 7654321Bit 0
= Unimplemented
Figure 11-2. TIM I/O Register Summary (Sheet 2 of 3)