Datasheet

Monitor ROM (MON)
MC68HC908LJ12 — Rev. 2.1 Technical Data
Freescale Semiconductor Monitor ROM (MON) 163
10.4.2 Data Format
Communication with the monitor ROM is in standard non-return-to-zero
(NRZ) mark/space data format. Transmit and receive baud rates must
be identical.
Figure 10-3. Monitor Data Format
10.4.3 Break Signal
A start bit (logic 0) followed by nine logic 0 bits is a break signal. When
the monitor receives a break signal, it drives the PTA0 pin high for the
duration of two bits and then echoes back the break signal.
Figure 10-4. Break Transaction
10.4.4 Baud Rate
The communication baud rate is controlled by the crystal frequency and
the state of the PTC1 pin (when IRQ
is set to V
TST
) upon entry into
monitor mode. When PTC1 is high, the divide by ratio is 1024. If the
PTC1 pin is at logic 0 upon entry into monitor mode, the divide by ratio
is 512.
If monitor mode was entered with V
DD
on IRQ, then the divide by ratio is
set at 1024, regardless of PTC1. If monitor mode was entered with V
SS
on IRQ, then the internal PLL steps up the external frequency, presumed
to be 32.768 kHz, to 2.4576 MHz. These latter two conditions for monitor
mode entry require that the reset vector is blank.
BIT 5
START
BIT
BIT 0 BIT 1
NEXT
STOP
BIT
START
BIT
BIT 2 BIT 3 BIT 4 BIT 6 BIT 7
0 1 2 3 4 5 6 7
0 1 2 3 4 5 6 7
MISSING STOP BIT
2-STOP BIT DELAY BEFORE ZERO ECHO