Datasheet

Monitor ROM (MON)
MC68HC908LJ12 — Rev. 2.1 Technical Data
Freescale Semiconductor Monitor ROM (MON) 161
NOTE: If the reset vector is blank and monitor mode is entered, the chip will see
an additional reset cycle after the initial POR reset. Once the part has
been programmed, the traditional method of applying a voltage, V
TST
, to
IRQ
must be used to enter monitor mode.
The COP module is disabled in monitor mode based on these
conditions:
• If monitor mode was entered as a result of the reset vector being
blank (above condition set 2 or 3), the COP is always disabled
regardless of the state of IRQ or RST.
• If monitor mode was entered with V
TST
on IRQ (condition set 1),
then the COP is disabled as long as V
TST
is applied to either IRQ
or RST.
The second condition states that as long as V
TST
is maintained on the
IRQ pin after entering monitor mode, or if V
TST
is applied to RST after
the initial reset to get into monitor mode (when V
TST
was applied to IRQ),
then the COP will be disabled. In the latter situation, after V
TST
is applied
to the RST pin, V
TST
can be removed from the IRQ pin in the interest of
freeing the IRQ for normal functionality in monitor mode.
Figure 10-2 shows a simplified diagram of the monitor mode entry when
the reset vector is blank and just 1 × V
DD
voltage is applied to the IRQ
pin. An external oscillator of 9.8304 MHz is required for a baud rate of
9600, as the internal bus frequency is automatically set to the external
frequency divided by four.
Enter monitor mode with pin configuration shown in Figure 10-1 by
pulling RST
low and then high. The rising edge of RST latches monitor
mode. Once monitor mode is latched, the values on the specified pins
can change.
Once out of reset, the MCU waits for the host to send eight security
bytes. (See 10.5 Security.) After the security bytes, the MCU sends a
break signal (10 consecutive logic 0s) to the host, indicating that it is
ready to receive a command.