Datasheet

Monitor ROM (MON) Technical Data MC68HC908LJ12 — Rev. 2.1
160 Monitor ROM (MON) Freescale Semiconductor
Table 10-1. Monitor Mode Signal Requirements and Options
IRQ RST
Address
$FFFE/
$FFFF
PTA2 PTA1 PTA0
(1)
PTC1
External
Clock
(2)
Bus
Frequency
PLL COP
Baud
Rate
Comment
XGNDX XXXX X 0 XDisabled0No operation until
reset goes high
V
TST
(3)
V
DD
or
V
TST
X 01104.9152
MHz
2.4576
MHz
OFF Disabled 9600 PTA1 and PTA2
voltages only
required if
IRQ
= V
TST
;
PTC1 determines
frequency divider
V
TST
(3)
V
DD
or
V
TST
X 01119.8304
MHz
2.4576
MHz
OFF Disabled 9600 PTA1 and PTA2
voltages only
required if
IRQ
= V
TST
;
PTC1 determines
frequency divider
V
DD
V
DD
Blank
"$FFFF"
X X 1 X 9.8304
MHz
2.4576
MHz
OFF Disabled 9600 External frequency
always divided by 4
GND V
DD
Blank
"$FFFF"
X X 1 X 32.768
kHz
2.4576
MHz
ON Disabled 9600 PLL enabled
(BCS set)
in monitor code
V
DD
or
GND
V
TST
Blank
"$FFFF"
XXXX X — OFFEnabled—Enters user
mode — will
encounter an illegal
address reset
V
DD
or
GND
V
DD
or
V
TST
Not BlankXXXX X — OFFEnabled—Enters user mode
Notes:
1. PTA0 = 1 if serial communication; PTA0 = 0 if parallel communication
2. External clock is derived by a 32.768 kHz crystal or a 4.9152/9.8304 MHz off-chip oscillator
3. Monitor mode entry by IRQ
= V
TST
, a 4.9152/9.8304 MHz off-chip oscillator must be used. The MCU internal crystal oscillator circuit is bypassed.