Datasheet

System Integration Module (SIM)
Technical Data MC68HC908LJ12 — Rev. 2.1
152 System Integration Module (SIM) Freescale Semiconductor
9.8.1 SIM Break Status Register
The SIM break status register (SBSR) contains a flag to indicate that a
break caused an exit from stop mode or wait mode.
SBSW — Break Wait Bit
This status bit is set when a break interrupt causes an exit from wait
mode or stop mode. Clear SBSW by writing a logic 0 to it. Reset clears
SBSW.
1 = Stop mode or wait mode was exited by break interrupt
0 = Stop mode or wait mode was not exited by break interrupt
SBSW can be read within the break interrupt routine. The user can
modify the return address on the stack by subtracting 1 from it. The
following code is an example.
Address: $FE00
Bit 7654321Bit 0
Read:
RRRRRR
SBSW
R
Write: Note
Reset: 0
Note: Writing a logic 0 clears SBSW.
R= Reserved
Figure 9-20. SIM Break Status Register (SBSR)
This code works if the H register has been pushed onto the stack in the break
service routine software. This code should be executed at the end of the break
service routine software.
HIBYTE EQU
LOBYTE EQU
If not SBSW, do RTI
BRCLR SBSW,SBSR, RETURN ;
;
See if wait mode or stop mode was exited by
break.
TST LOBYTE,SP ;If RETURNLO is not zero,
BNE DOLO ;then just decrement low byte.
DEC HIBYTE,SP ;Else deal with high byte, too.
DOLO DEC LOBYTE,SP ;Point to WAIT/STOP opcode.
RETURN PULH
RTI
;Restore H register.