Datasheet

System Integration Module (SIM)
MC68HC908LJ12 — Rev. 2.1 Technical Data
Freescale Semiconductor System Integration Module (SIM) 135
Figure 9-3. CGM Clock Signals
9.3.1 Bus Timing
In user mode, the internal bus frequency is either the oscillator output
(CGMXCLK) divided by four, CGMXCLK divided by two, or the PLL
output (CGMPCLK) divided by four.
9.3.2 Clock Start-up from POR or LVI Reset
When the power-on reset module or the low-voltage inhibit module
generates a reset, the clocks to the CPU and peripherals are inactive
and held in an inactive phase until after the 4096 ICLK cycle POR
timeout has completed. The RST pin is driven low by the SIM during this
entire period. The IBUS clocks start upon completion of the timeout.
÷ 2
BUS CLOCK
GENERATORS
SYSTEM INTEGRATION MODULE
MONITOR MODE
USER MODE
SIMOSCEN
OSCILLATOR (OSC) MODULE
OSC2
OSC1
PHASE-LOCKED LOOP (PLL)
CGMXCLK
CGMRCLK
IT12
CGMOUT
SIMDIV2
PTC1
TO RTC, ADC
STOP MODE CLOCK
TO REST
OF MCU
IT23
TO REST
OF MCU
ENABLE SIGNALS
FROM CONFIG2
ICLK
SIM COUNTER