Datasheet

System Integration Module (SIM)
Technical Data MC68HC908LJ12 — Rev. 2.1
134 System Integration Module (SIM) Freescale Semiconductor
9.3 SIM Bus Clock Control and Generation
The bus clock generator provides system clock signals for the CPU and
peripherals on the MCU. The system clocks are generated from an
incoming clock, CGMOUT, as shown in Figure 9-3. This clock can come
from either the oscillator module or from the on-chip PLL. (See Section
8. Clock Generator Module (CGM).)
Addr.Register Name Bit 7654321Bit 0
$FE00
SIM Break Status Register
(SBSR)
Read:
RRRRRR
SBSW
R
Write: Note
Reset: 0
Note: Writing a logic 0 clears SBSW.
$FE01
SIM Reset Status Register
(SRSR)
Read: POR PIN COP ILOP ILAD 0 LVI 0
Write:
POR:10000000
$FE03
SIM Break Flag Control
Register
(SBFCR)
Read:
BCFERRRRRRR
Write:
Reset: 0
$FE04
Interrupt Status Register 1
(INT1)
Read: IF6 IF5 IF4 IF3 IF2 IF1 0 0
Write:RRRRRRRR
Reset:00000000
$FE05
Interrupt Status Register 2
(INT2)
Read: IF14 IF13 IF12 IF11 IF10 IF9 IF8 IF7
Write:RRRRRRRR
Reset:00000000
$FE06
Interrupt Status Register 3
(INT3)
Read: 00000IF17IF16IF15
Write:RRRRRRRR
Reset:00000000
= Unimplemented R = Reserved
Figure 9-2. SIM I/O Register Summary