Datasheet

System Integration Module (SIM)
MC68HC908LJ12 — Rev. 2.1 Technical Data
Freescale Semiconductor System Integration Module (SIM) 133
Figure 9-1. SIM Block Diagram
STOP/WAIT
CLOCK
CONTROL
CLOCK GENERATORS
POR CONTROL
RESET PIN CONTROL
SIM RESET STATUS REGISTER
INTERRUPT CONTROL
AND PRIORITY DECODE
MODULE STOP
MODULE WAIT
CPU STOP (FROM CPU)
CPU WAIT (FROM CPU)
SIMOSCEN (TO CGM, OSC)
CGMOUT (FROM CGM)
INTERNAL CLOCKS
MASTER
RESET
CONTROL
RESET
PIN LOGIC
LVI (FROM LVI MODULE)
ILLEGAL OPCODE (FROM CPU)
ILLEGAL ADDRESS (FROM ADDRESS
MAP DECODERS)
COP (FROM COP MODULE)
INTERRUPT SOURCES
CPU INTERFACE
RESET
CONTROL
SIM
COUNTER
COP CLOCK
ICLK (FROM OSC)
÷ 2
V
DD
INTERNAL
PULLUP
DEVICE
Table 9-1. Signal Name Conventions
Signal Name Description
ICLK Internal RC oscillator clock
CGMXCLK Buffered version of OSC1 from the oscillator module
CGMPCLK PLL output and the divided PLL output
CGMOUT
PLL-based or oscillator-based clock output from CGM module
(Bus clock = CGMOUT ÷ 2)
IAB Internal address bus
IDB Internal data bus
PORRST Signal from the power-on reset module to the SIM
IRST Internal reset signal
R/W
Read/write signal