Datasheet

System Integration Module (SIM)
Technical Data MC68HC908LJ12 — Rev. 2.1
132 System Integration Module (SIM) Freescale Semiconductor
9.6.4 Status Flag Protection in Break Mode . . . . . . . . . . . . . . . .148
9.7 Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .149
9.7.1 Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .149
9.7.2 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .150
9.8 SIM Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .151
9.8.1 SIM Break Status Register. . . . . . . . . . . . . . . . . . . . . . . . .152
9.8.2 SIM Reset Status Register . . . . . . . . . . . . . . . . . . . . . . . .153
9.8.3 SIM Break Flag Control Register . . . . . . . . . . . . . . . . . . . .154
9.2 Introduction
This section describes the system integration module (SIM). Together
with the CPU, the SIM controls all MCU activities. A block diagram of the
SIM is shown in Figure 9-1. Table 9-1 is a summary of the SIM
input/output (I/O) registers. The SIM is a system state controller that
coordinates CPU and exception timing. The SIM is responsible for:
• Bus clock generation and control for CPU and peripherals:
– Stop/wait/reset/break entry and recovery
– Internal clock control
• Master reset control, including power-on reset (POR) and COP
timeout
• Interrupt control:
– Acknowledge timing
– Arbitration control timing
– Vector address generation
• CPU enable/disable timing
• Modular architecture expandable to 128 interrupt sources
Table 9-1 shows the internal signal names used in this section.