Datasheet

Clock Generator Module (CGM)
Technical Data MC68HC908LJ12 — Rev. 2.1
124 Clock Generator Module (CGM) Freescale Semiconductor
8.6.5 PLL Reference Divider Select Register
The PLL reference divider select register (PMDS) contains the
programming information for the modulo reference divider.
RDS[3:0] — Reference Divider Select Bits
These read/write bits control the modulo reference divider that selects
the reference division factor, R. (See 8.4.3 PLL Circuits and 8.4.6
Programming the PLL.) RDS[3:0] cannot be written when the
PLLON bit in the PCTL is set. A value of $00 in the reference divider
select register configures the reference divider the same as a value of
$01. (See 8.4.7 Special Programming Exceptions.) Reset
initializes the register to $01 for a default divide value of 1.
NOTE: The reference divider select bits have built-in protection such that they
cannot be written when the PLL is on (PLLON = 1).
NOTE: The default divide value of 1 is recommended for all applications.
Address: $003B
Bit 7654321Bit 0
Read: 0 0 0 0
RDS3 RDS2 RDS1 RDS0
Write:
Reset:
0
00
0
0001
= Unimplemented
Figure 8-9. PLL Reference Divider Select Register (PMDS)