Datasheet

Clock Generator Module (CGM)
MC68HC908LJ12 — Rev. 2.1 Technical Data
Freescale Semiconductor Clock Generator Module (CGM) 123
8.6.4 PLL VCO Range Select Register
The PLL VCO range select register (PMRS) contains the programming
information required for the hardware configuration of the VCO.
VRS[7:0] — VCO Range Select Bits
These read/write bits control the hardware center-of-range linear
multiplier L which, in conjunction with E (See 8.4.3 PLL Circuits,
8.4.6 Programming the PLL, and 8.6.1 PLL Control Register.),
controls the hardware center-of-range frequency, f
VRS
. VRS[7:0]
cannot be written when the PLLON bit in the PCTL is set. (See 8.4.7
Special Programming Exceptions.) A value of $00 in the VCO
range select register disables the PLL and clears the BCS bit in the
PLL control register (PCTL). (See 8.4.8 Base Clock Selector Circuit
and 8.4.7 Special Programming Exceptions.). Reset initializes the
register to $40 for a default range multiply value of 64.
NOTE: The VCO range select bits have built-in protection such that they cannot
be written when the PLL is on (PLLON = 1) and such that the VCO clock
cannot be selected as the source of the base clock (BCS = 1) if the VCO
range select bits are all clear.
The PLL VCO range select register must be programmed correctly.
Incorrect programming can result in failure of the PLL to achieve lock.
Address: $003A
Bit 7654321Bit 0
Read:
VRS7 VRS6 VRS5 VRS4 VRS3 VRS2 VRS1 VRS0
Write:
Reset:01000000
Figure 8-8. PLL VCO Range Select Register (PMRS)