Datasheet

Clock Generator Module (CGM)
Technical Data MC68HC908LJ12 — Rev. 2.1
122 Clock Generator Module (CGM) Freescale Semiconductor
8.6.3 PLL Multiplier Select Registers
The PLL multiplier select registers (PMSH and PMSL) contain the
programming information for the modulo feedback divider.
MUL[11:0] — Multiplier Select Bits
These read/write bits control the modulo feedback divider that selects
the VCO frequency multiplier N. (See 8.4.3 PLL Circuits and 8.4.6
Programming the PLL.) A value of $0000 in the multiplier select
registers configure the modulo feedback divider the same as a value
of $0001. Reset initializes the registers to $0040 for a default multiply
value of 64.
NOTE: The multiplier select bits have built-in protection such that they cannot
be written when the PLL is on (PLLON = 1).
Address: $0038
Bit 7654321Bit 0
Read: 0 0 0 0
MUL11 MUL10 MUL9 MUL8
Write:
Reset:00000000
= Unimplemented
Figure 8-6. PLL Multiplier Select Register High (PMSH)
Address: $0039
Bit 7654321Bit 0
Read:
MUL7 MUL6 MUL5 MUL4 MUL3 MUL2 MUL1 MUL0
Write:
Reset:01000000
Figure 8-7. PLL Multiplier Select Register Low (PMSL)