Datasheet

Clock Generator Module (CGM)
Technical Data MC68HC908LJ12 — Rev. 2.1
120 Clock Generator Module (CGM) Freescale Semiconductor
VPR1 and VPR0 — VCO Power-of-Two Range Select Bits
These read/write bits control the VCO’s hardware power-of-two range
multiplier E that, in conjunction with L (See 8.4.3 PLL Circuits, 8.4.6
Programming the PLL, and 8.6.4 PLL VCO Range Select
Register.) controls the hardware center-of-range frequency, f
VRS
.
VPR1:VPR0 cannot be written when the PLLON bit is set. Reset
clears these bits.
8.6.2 PLL Bandwidth Control Register
The PLL bandwidth control register (PBWC):
• Selects automatic or manual (software-controlled) bandwidth
control mode
• Indicates when the PLL is locked
• In automatic bandwidth control mode, indicates when the PLL is in
acquisition or tracking mode
• In manual operation, forces the PLL into acquisition or tracking
mode
Table 8-2. PRE 1 and PRE0 Programming
PRE1 and PRE0 P Prescaler Multiplier
00 0 1
01 1 2
10 2 4
11 3 8
Table 8-3. VPR1 and VPR0 Programming
VPR1 and VPR0 E
VCO Power-of-Two
Range Multiplier
00 0 1
01 1 2
10 2 4
NOTE: Do not program E to a value of 3.