Datasheet

Clock Generator Module (CGM)
Technical Data MC68HC908LJ12 — Rev. 2.1
116 Clock Generator Module (CGM) Freescale Semiconductor
8.5.1 External Filter Capacitor Pin (CGMXFC)
The CGMXFC pin is required by the loop filter to filter out phase
corrections. An external filter network is connected to this pin. (See
Figure 8-3.)
NOTE: To prevent noise problems, the filter network should be placed as close
to the CGMXFC pin as possible, with minimum routing distances and no
routing of other signals across the network.
8.5.2 PLL Analog Power Pin (V
DDA
)
V
DDA
is a power pin used by the analog portions of the PLL. Connect the
V
DDA
pin to the same voltage potential as the V
DD
pin.
NOTE: Route V
DDA
carefully for maximum noise immunity and place bypass
capacitors as close as possible to the package.
8.5.3 PLL Analog Ground Pin (V
SSA
)
V
SSA
is a ground pin used by the analog portions of the PLL. Connect
the V
SSA
pin to the same voltage potential as the V
SS
pin.
NOTE: Route V
SSA
carefully for maximum noise immunity and place bypass
capacitors as close as possible to the package.
NOTE: On this MCU, the V
SSA
is physically bonded to the V
SS
pin.
8.5.4 Oscillator Output Frequency Signal (CGMXCLK)
CGMXCLK is the oscillator output signal. It runs at the full speed of the
oscillator, and is generated directly from the crystal oscillator circuit, the
RC oscillator circuit, or the internal oscillator circuit.
8.5.5 CGM Reference Clock (CGMRCLK)
CGMRCLK is a buffered version of CGMXCLK, this clock is the
reference clock for the phase-locked-loop circuit.