Datasheet

Clock Generator Module (CGM)
Technical Data MC68HC908LJ12 — Rev. 2.1
114 Clock Generator Module (CGM) Freescale Semiconductor
8.4.7 Special Programming Exceptions
The programming method described in 8.4.6 Programming the PLL
does not account for three possible exceptions. A value of 0 for R, N, or
L is meaningless when used in the equations given. To account for these
exceptions:
• A 0 value for R or N is interpreted exactly the same as a value of 1.
• A 0 value for L disables the PLL and prevents its selection as the
source for the base clock.
(See 8.4.8 Base Clock Selector Circuit.)
8.4.8 Base Clock Selector Circuit
This circuit is used to select either the oscillator clock, CGMXCLK, or the
divided VCO clock, CGMPCLK, as the source of the base clock,
CGMOUT. The two input clocks go through a transition control circuit
that waits up to three CGMXCLK cycles and three CGMPCLK cycles to
change from one clock source to the other. During this time, CGMOUT
is held in stasis. The output of the transition control circuit is then divided
by two to correct the duty cycle. Therefore, the bus clock frequency,
which is one-half of CGMOUT, is one-fourth the frequency of the
selected clock (CGMXCLK or CGMPCLK).
For the CGMXCLK, the divide-by-2 can be by-passed by setting the
DIV2CLK bit in the CONFIG2 register. Therefore, the bus clock
frequency can be one-half of CGMXCLK.
The BCS bit in the PLL control register (PCTL) selects which clock drives
CGMOUT. The divided VCO clock cannot be selected as the base clock
source if the PLL is not turned on. The PLL cannot be turned off if the
divided VCO clock is selected. The PLL cannot be turned on or off
simultaneously with the selection or deselection of the divided VCO
clock. The divided VCO clock also cannot be selected as the base clock
source if the factor L is programmed to a 0. This value would set up a
condition inconsistent with the operation of the PLL, so that the PLL
would be disabled and the oscillator clock would be forced as the source
of the base clock.