Datasheet

Clock Generator Module (CGM)
Technical Data MC68HC908LJ12 — Rev. 2.1
112 Clock Generator Module (CGM) Freescale Semiconductor
6. Select the VCO’s power-of-two range multiplier E, according to
this table:
7. Select a VCO linear range multiplier, L, where f
NOM
= 38.4kHz
8. Calculate and verify the adequacy of the VCO programmed
center-of-range frequency, f
VRS
. The center-of-range frequency is
the midpoint between the minimum and maximum frequencies
attainable by the PLL.
For proper operation,
9. Verify the choice of P, R, N, E, and L by comparing f
VCLK
to f
VRS
and f
VCLKDES
. For proper operation, f
VCLK
must be within the
application’s tolerance of f
VCLKDES
, and f
VRS
must be as close as
possible to f
VCLK.
NOTE: Exceeding the recommended maximum bus frequency or VCO
frequency can crash the MCU.
Frequency Range E
0 < f
VCLK
< 9,830,400
0
9,830,400 ≤ f
VCLK
< 19,660,800
1
19,660,800 ≤ f
VCLK
< 39,321,600
2
NOTE: Do not program E to a value of 3.
L round
f
VCLK
2
E
f
NOM
×
--------------------------



=
f
VRS
L2
E
×()f
NOM
=
f
VRS
f
VCLK
–
f
NOM
2
E
×
2
--------------------------≤