Datasheet

Clock Generator Module (CGM)
MC68HC908LJ12 — Rev. 2.1 Technical Data
Freescale Semiconductor Clock Generator Module (CGM) 111
The relationship between the VCO frequency, f
VCLK
, and the
reference frequency, f
RCLK
, is
where N is the integer range multiplier, between 1 and 4095.
In cases where desired bus frequency has some tolerance,
choose f
RCLK
to a value determined either by other module
requirements (such as modules which are clocked by CGMXCLK),
cost requirements, or ideally, as high as the specified range
allows. See Section 23. Electrical Specifications. Choose the
reference divider, R = 1.
When the tolerance on the bus frequency is tight, choose f
RCLK
to
an integer divisor of f
BUSDES
, and R = 1. If f
RCLK
cannot meet this
requirement, use the following equation to solve for R with
practical choices of f
RCLK
, and choose the f
RCLK
that gives the
lowest R.
4. Calculate N:
5. Calculate and verify the adequacy of the VCO and bus
frequencies f
VCLK
and f
BUS
.
f
VCLK
2
P
N
R
----------- f
RCLK
()=
R round R
MAX
f
VCLKDES
f
RCLK
--------------------------



integer
f
VCLKDES
f
RCLK
--------------------------



–



×=
N round
Rf
VCLKDES
×
f
RCLK
2
P
×
-------------------------------------



=
f
BUS
f
VCLK
2
P
4×
-----------
=
f
VCLK
2
P
N
R
----------- f
RCLK
()=