Datasheet

Clock Generator Module (CGM)
MC68HC908LJ12 — Rev. 2.1 Technical Data
Freescale Semiconductor Clock Generator Module (CGM) 109
The following conditions apply when the PLL is in automatic bandwidth
control mode:
• The ACQ bit (See 8.6.2 PLL Bandwidth Control Register.) is a
read-only indicator of the mode of the filter. (See 8.4.4
Acquisition and Tracking Modes.)
• The ACQ bit is set when the VCO frequency is within a certain
tolerance and is cleared when the VCO frequency is out of a
certain tolerance. (See 8.9 Acquisition/Lock Time
Specifications for more information.)
• The LOCK bit is a read-only indicator of the locked state of the
PLL.
• The LOCK bit is set when the VCO frequency is within a certain
tolerance and is cleared when the VCO frequency is out of a
certain tolerance. (See 8.9 Acquisition/Lock Time
Specifications for more information.)
• CPU interrupts can occur if enabled (PLLIE = 1) when the PLL’s
lock condition changes, toggling the LOCK bit. (See 8.6.1 PLL
Control Register.)
The PLL also may operate in manual mode (AUTO = 0). Manual mode
is used by systems that do not require an indicator of the lock condition
for proper operation. Such systems typically operate well below
f
BUSMAX
.