Datasheet

Clock Generator Module (CGM)
Technical Data MC68HC908LJ12 — Rev. 2.1
108 Clock Generator Module (CGM) Freescale Semiconductor
8.4.4 Acquisition and Tracking Modes
The PLL filter is manually or automatically configurable into one of two
operating modes:
• Acquisition mode — In acquisition mode, the filter can make large
frequency corrections to the VCO. This mode is used at PLL start
up or when the PLL has suffered a severe noise hit and the VCO
frequency is far off the desired frequency. When in acquisition
mode, the ACQ bit is clear in the PLL bandwidth control register.
(See 8.6.2 PLL Bandwidth Control Register.)
• Tracking mode — In tracking mode, the filter makes only small
corrections to the frequency of the VCO. PLL jitter is much lower
in tracking mode, but the response to noise is also slower. The
PLL enters tracking mode when the VCO frequency is nearly
correct, such as when the PLL is selected as the base clock
source. (See 8.4.8 Base Clock Selector Circuit.) The PLL is
automatically in tracking mode when not in acquisition mode or
when the ACQ bit is set.
8.4.5 Manual and Automatic PLL Bandwidth Modes
The PLL can change the bandwidth or operational mode of the loop filter
manually or automatically. Automatic mode is recommended for most
users.
In automatic bandwidth control mode (AUTO = 1), the lock detector
automatically switches between acquisition and tracking modes.
Automatic bandwidth control mode also is used to determine when the
VCO clock, CGMVCLK, is safe to use as the source for the base clock,
CGMOUT. (See 8.6.2 PLL Bandwidth Control Register.) If PLL
interrupts are enabled, the software can wait for a PLL interrupt request
and then check the LOCK bit. If interrupts are disabled, software can poll
the LOCK bit continuously (during PLL start-up, usually) or at periodic
intervals. In either case, when the LOCK bit is set, the VCO clock is safe
to use as the source for the base clock. (See 8.4.8 Base Clock Selector
Circuit.) If the VCO is selected as the source for the base clock and the
LOCK bit is clear, the PLL has suffered a severe noise hit and the
software must take appropriate action, depending on the application.
(See 8.7 Interrupts for information and precautions on using interrupts.)