Datasheet

Clock Generator Module (CGM)
Technical Data MC68HC908LJ12 — Rev. 2.1
104 Clock Generator Module (CGM) Freescale Semiconductor
Figure 8-1. CGM Block Diagram
BCS
PHASE
DETECTOR
LOOP
FILTER
FREQUENCY
DIVIDER
VOLTAGE
CONTROLLED
OSCILLATOR
AUTOMATIC
MODE
CONTROL
LOCK
DETECTOR
CGMXCLK
CGMOUT
CGMVDV
INTERRUPT
CONTROL
CGMINT
CGMRDV
PLL ANALOG
CGMRCLK
V
DDA
CGMXFC V
SSA
LOCK AUTO ACQ
VPR[1:0]
PLLIE PLLF
MUL[11:0]
REFERENCE
DIVIDER
VRS[7:0]
FREQUENCY
DIVIDER
PRE[1:0]
T0 RTC, ADC, LCD
PHASE-LOCKED LOOP (PLL)
A
B
1
S
CONFIG2
To SIM
To SIM
RDS[3:0]
R
CGMPCLK
SIMOSCEN
OSCILLATOR (OSC) MODULE
OSC2
OSC1
From SIM
ICLK
CGMRCLK
INTERNAL RC OSC
CRYSTAL OSCILLATOR
See Section 7. Oscillator (OSC).
N
To SIM (and COP)
L
2
P
2
E
SIMDIV2
From SIM
DIV2CLK
A
B
1
S
÷ 2
A
B
1
S
USER MODE:
CGMOUT = B
RESET: A
RESET: A
CGMPCLK
CLOCK
SELECT
CIRCUIT
CGMVCLK
BASE