Datasheet

Clock Generator Module (CGM)
Technical Data MC68HC908LJ12 — Rev. 2.1
102 Clock Generator Module (CGM) Freescale Semiconductor
8.7 Interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .125
8.8 Special Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .125
8.8.1 Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .125
8.8.2 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .126
8.8.3 CGM During Break Interrupts. . . . . . . . . . . . . . . . . . . . . . .126
8.9 Acquisition/Lock Time Specifications . . . . . . . . . . . . . . . . . . .127
8.9.1 Acquisition/Lock Time Definitions. . . . . . . . . . . . . . . . . . . .127
8.9.2 Parametric Influences on Reaction Time . . . . . . . . . . . . . .127
8.9.3 Choosing a Filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .129
8.2 Introduction
This section describes the clock generator module (CGM). The CGM
generates the base clock signal, CGMOUT, which is based on either the
oscillator clock divided by two or the divided phase-locked loop (PLL)
clock, CGMPCLK, divided by two. CGMOUT is the clock from which the
SIM derives the system clocks, including the bus clock, which is at a
frequency of CGMOUT÷2.
The PLL is a frequency generator designed for use with a low frequency
crystal (typically 32.768kHz) to generate a base frequency and dividing
to a maximum bus frequency of 8MHz.