Datasheet

LVI Status Register
MC68HC908QY/QT Family Data Sheet, Rev. 6
Freescale Semiconductor 87
10.4 LVI Status Register
The LVI status register (LVISR) indicates if the V
DD
voltage was detected below the V
TRIPF
level while
LVI resets have been disabled
.
LVIOUT — LVI Output Bit
This read-only flag becomes set when the V
DD
voltage falls below the V
TRIPF
trip voltage and is cleared
when V
DD
voltage rises above V
TRIPR
. The difference in these threshold levels results in a hysteresis
that prevents oscillation into and out of reset (see Table 10-1). Reset clears the LVIOUT bit.
10.5 LVI Interrupts
The LVI module does not generate interrupt requests.
10.6 Low-Power Modes
The STOP and WAIT instructions put the MCU in low power-consumption standby modes.
10.6.1 Wait Mode
If enabled, the LVI module remains active in wait mode. If enabled to generate resets, the LVI module can
generate a reset and bring the MCU out of wait mode.
10.6.2 Stop Mode
When the LVIPWRD bit in the configuration register is cleared and the LVISTOP bit in the configuration
register is set, the LVI module remains active in stop mode. If enabled to generate resets, the LVI module
can generate a reset and bring the MCU out of stop mode.
Address: $FE0C
Bit 7654321Bit 0
Read:LVIOUT000000R
Write:
Reset:00000000
= Unimplemented R = Reserved
Figure 10-2. LVI Status Register (LVISR)
Table 10-1. LVIOUT Bit Indication
V
DD
LVIOUT
V
DD
> V
TRIPR
0
V
DD
< V
TRIPF
1
V
TRIPF
< V
DD
< V
TRIPR
Previous value