Datasheet

Low-Voltage Inhibit (LVI)
MC68HC908QY/QT Family Data Sheet, Rev. 6
86 Freescale Semiconductor
V
TRIPF
. Setting the LVI enable in stop mode bit, LVISTOP, enables the LVI to operate in stop mode.
Setting the LVI 5-V or 3-V trip point bit, LVI5OR3, enables the trip point voltage, V
TRIPF
, to be configured
for 5-V operation. Clearing the LVI5OR3 bit enables the trip point voltage, V
TRIPF
, to be configured for 3-V
operation. The actual trip thresholds are specified in 16.5 5-V DC Electrical Characteristics and 16.9 3-V
DC Electrical Characteristics.
NOTE
After a power-on reset, the LVI’s default mode of operation is 3 volts. If a
5-V system is used, the user must set the LVI5OR3 bit to raise the trip point
to 5-V operation.
If the user requires 5-V mode and sets the LVI5OR3 bit after power-on reset
while the V
DD
supply is not above the V
TRIPR
for 5-V mode, the
microcontroller unit (MCU) will immediately go into reset. The next time the
LVI releases the reset, the supply will be above the V
TRIPR
for 5-V mode.
Once an LVI reset occurs, the MCU remains in reset until V
DD
rises above a voltage, V
TRIPR
, which
causes the MCU to exit reset. See Chapter 13 System Integration Module (SIM) for the reset recovery
sequence.
The output of the comparator controls the state of the LVIOUT flag in the LVI status register (LVISR) and
can be used for polling LVI operation when the LVI reset is disabled.
10.3.1 Polled LVI Operation
In applications that can operate at V
DD
levels below the V
TRIPF
level, software can monitor V
DD
by polling
the LVIOUT bit. In the configuration register, the LVIPWRD bit must be cleared to enable the LVI module,
and the LVIRSTD bit must be at set to disable LVI resets.
10.3.2 Forced Reset Operation
In applications that require V
DD
to remain above the V
TRIPF
level, enabling LVI resets allows the LVI
module to reset the MCU when V
DD
falls below the V
TRIPF
level. In the configuration register, the
LVIPWRD and LVIRSTD bits must be cleared to enable the LVI module and to enable LVI resets.
10.3.3 Voltage Hysteresis Protection
Once the LVI has triggered (by having V
DD
fall below V
TRIPF
), the LVI will maintain a reset condition until
V
DD
rises above the rising trip point voltage, V
TRIPR
. This prevents a condition in which the MCU is
continually entering and exiting reset if V
DD
is approximately equal to V
TRIPF
. V
TRIPR
is greater than
V
TRIPF
by the hysteresis voltage, V
HYS
.
10.3.4 LVI Trip Selection
The LVI5OR3 bit in the configuration register selects whether the LVI is configured for 5-V or 3-V
protection.
NOTE
The microcontroller is guaranteed to operate at a minimum supply voltage.
The trip point (V
TRIPF
[5 V] or V
TRIPF
[3 V]) may be lower than this.
See 16.5 5-V DC Electrical Characteristics and 16.9 3-V DC Electrical
Characteristics for the actual trip point voltages.