Datasheet

MC68HC908QY/QT Family Data Sheet, Rev. 6
Freescale Semiconductor 85
Chapter 10
Low-Voltage Inhibit (LVI)
10.1 Introduction
This section describes the low-voltage inhibit (LVI) module, which monitors the voltage on the V
DD
pin
and can force a reset when the V
DD
voltage falls below the LVI trip falling voltage, V
TRIPF
.
10.2 Features
Features of the LVI module include:
• Programmable LVI reset
• Programmable power consumption
• Selectable LVI trip voltage
• Programmable stop mode operation
10.3 Functional Description
Figure 10-1 shows the structure of the LVI module. LVISTOP, LVIPWRD, LVI5OR3, and LVIRSTD are
user selectable options found in the configuration register (CONFIG1). See Chapter 5 Configuration
Register (CONFIG).
Figure 10-1. LVI Module Block Diagram
The LVI is enabled out of reset. The LVI module contains a bandgap reference circuit and comparator.
Clearing the LVI power disable bit, LVIPWRD, enables the LVI to monitor V
DD
voltage. Clearing the LVI
reset disable bit, LVIRSTD, enables the LVI module to generate a reset when V
DD
falls below a voltage,
LOW V
DD
DETECTOR
LVIPWRD
STOP INSTRUCTION
LVISTOP
LVI RESET
LVIOUT
V
DD
> LVITRIP = 0
V
DD
≤ LVITRIP = 1
FROM CONFIG
FROM CONFIG
V
DD
FROM CONFIG
LVIRSTD
LVI5OR3
FROM CONFIG